1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display with a simplified data driving circuit structure and a method of driving the liquid crystal display.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) displays a picture using an electric field to control light transmittance of a liquid crystal. To this end, the LCD includes an LCD panel having liquid crystal cells arranged in a matrix type, and a driving circuit for driving the LCD panel. The LCD is readily designed to have a dimension much smaller than any CRT tube to meet market's desires for a display device installed in a portable television, a lap-top personal computer, or the like.
FIG. 1 is a schematic block circuit diagram illustrating a configuration of a related art LCD. As shown in FIG. 1, the related art LCD includes an LCD panel 2 having liquid crystal cells arranged in a matrix form, a data driver 4 for driving data lines DL1 through DLm of the LCD panel 2, a gate driver 6 for driving gate lines GL1 through GLn of the LCD panel 2, a timing controller 8 for controlling the data and gate drivers 4 and 6, and a reference gamma voltage generator 9 for supplying 16 reference gamma voltages GM1 through GMA16 to the data driver 4.
The LCD panel 2 includes a thin film transistor TFT provided at each intersection between the data lines DL1 through DLm and gate lines GL1 through GLn, and a liquid crystal cell 7 connected to the thin film transistor TFT. The thin film transistor TFT is turned on at the time of receiving a scanning signal, namely, a gate high voltage VGH from the gate line GL, thereby applying an analog data from the data line DL to the liquid crystal cell 7. On the other hand, the thin film transistor TFT is turned off at the time of receiving a gate low voltage VGL from the gate line GL, thereby keeping the analog data charged in the liquid crystal cell 7.
The liquid crystal cell 7 may be equivalently regarded as a liquid crystal capacitor. The liquid crystal cell 7 includes a common electrode and a pixel electrode connected to the thin film transistor. The common electrode and pixel electrode are opposed to each other and a liquid crystal is arranged therebetween. Also, the liquid crystal cell 7 includes a storage capacitor for keeping a stable maintenance of the charged analog data signal until the analog data is charged. This storage capacitor is provided between the pixel electrode and a pre-stage gate line. The liquid crystal cell 7 varies an alignment state of the liquid crystal having a dielectric anisotropy in accordance with analog data charged through the thin film transistor TFT to control light transmittance, thereby implementing gray scale levels.
FIG. 2 is a block diagram of the timing controller 8 of FIG. 1. As shown in FIG. 2, the timing controller 8 generates gate control signals (i.e., GSP, GSC, GOE, etc.) for controlling the gate driver 6, and data control signals (i.e., SSP, SSC, SOE, POL, etc.) for controlling the data driver 4 based on various control signals DE, Hsync, Vsync and DCLK supplied externally. Also, the timing controller 8 aligns 8-bit data RGB supplied externally for driving the LCD panel 2, and applies them to the data driver 4. Specifically, the timing controller 8 includes a data processor 32 for aligning the external 8-bit data so that they are suitable for driving the LCD panel 2 and re-arranging them, and a control signal generator 34 for utilizing the various external control signals to generate the gate control signals GSP, GSC, GOE, etc. as well as the data control signals SSP, SSC, SOE, POL, REV, etc.
More specifically, the data processor 32 aligns the 8-bit data into odd data ODD Data and even data EVEN Data so that they are suitable for driving the LCD panel 2, and supplies aligned data Data to the data driver 4. The control signal generator 34 generates the data control signals SSP, SSC, SOE, POL, REV, etc. to apply them to the data driver 4 and, at the same time, generates the gate control signals GSC, GSP, GOE, etc. to apply them to the gate driver 6 with the aid of a data enable signal DE informing an effective data interval, a horizontal synchronizing signal Hsync, a frame frequency Vsync and a dot clock DCLK for determining a transmission timing of the aligned data Data.
To sequentially drive the gate lines GL1 through GLn, the gate driver 6 is provided with a plurality of gate driving integrated circuits (ICs) (not shown). The gate driving ICs sequentially drive the gate lines GL1 through GLn under control of the timing controller 8. In other words, the gate ICs sequentially apply a gate high voltage VGH to the gate lines GL1 through GLn in response to the gate control signals GSP, GSC, GOE, etc. from the timing controller 8. The reference gamma voltage generator 9 generates the 16 reference gamma voltages GM1 through GMA16 having different voltage levels and supplies them to the data driver 4.
To apply analog data to each of the data lines DL1 through DLm every horizontal period (i.e., 16.67 ms when the frame frequency Vsync is 60 Hz), the data driver 4 is provided with a plurality of data driving ICs (not shown). The data driving ICs apply analog data to the data lines DL1 through DLm in response to the data control signals SSP, SSC, SOE, REV, POL, etc. from the timing controller 8. FIG. 3 is a block diagram of the data driver 4 of FIG. 1. As shown in FIG. 3, each of the data driving ICs includes a shift register portion 14 for applying sequential sampling signals, a latch portion 16 for sequentially latching the digital data Data in response to the sampling signals to output them simultaneously, a digital to analog converter (DAC) 18 for converting the digital data Data from the latch portion 16 into analog data AData, and an output buffer portion 26 for buffering and outputting the analog data AData.
Also, the data driver 4 includes a signal generator 10 for relaying the data control signals SSP, SSC, SOE, REV, POL, etc. and the digital data Data, and a gamma voltage part 12 for supplying positive and negative gamma voltages required for the DAC 18. Each of the data driving ICs drives each of the data lines DL1 through DLn. The signal generator 10 controls the various control signals SSP, SSC, SOE, REV, POL, etc. and the digital Data to output them to their corresponding elements.
The gamma voltage part 12 sub-divides the 16 reference gamma voltages GM1 through GMA16 for each gray level using an internal R-String and outputs them. FIG. 4 is a circuit diagram of the gamma voltage part 12 of FIG. 3. As shown in FIG. 4, the gamma voltage part 12 outputs 256 positive gamma voltages V0 through V255 having different voltage levels from each of nodes between the internal R-string to the DAC 18. That is, a plurality of resistors R1 through R257 are connected in series between a supply voltage source VDD and a ground voltage source GND. Further, the gamma voltage part 12 generates 256 negative gamma voltages (not shown) and supplies them to the DAC 18. The shift register portion 14 includes n shift registers for sequentially shifting a source start pulse SSP from the signal generator 10 in response to a source sampling clock signal SSC, and output the source start pulse SSP as a sampling signal.
To sequentially sample the digital data Data from the signal generator 10 for a certain unit in response to the sampling signals to latch them, the latch portion 16 is provided with n latches to latch n digital data Data, wherein each of the latches has a dimension corresponding to the bit number of the digital data Data. Particularly, the timing controller 8 divides the digital data Data into the even data EVEN Data and the odd data ODD Data so as to reduce a transmission frequency, and simultaneously outputs them over each transmission line. Herein, each of the even data EVEN Data and the odd data ODD Data includes red (R), green (G) and blue (B) data. Thus, the latch portion 16 simultaneously latches the even data EVEN Data and the odd data ODD Data, namely, 6 digital data Data supplied via the signal generator 10 for each sampling signal. Then, the latch portion 16 simultaneously outputs the n latched data Data in response to a source output enable signal SOE from the signal generator 10. Herein, the latch portion 16 restores the digital data Data modulated such that the transition bit number is reduced in response to a data inversion selection signal REV, and outputs them. Specifically, the timing controller 8 modulates the digital data Data having the transited bit number going beyond a reference value such that the transition bit number is reduced, thereby minimizing an electromagnetic interference (EMI) upon data transmission.
To simultaneously convert the digital data Data from the latch portion 16 into the positive and negative analog data AData and output them, as shown in FIG. 3, the DAC 18 is provided with a positive (P) decoding part 20 and a negative (N) decoding part 22 commonly connected to the latch portion 16, and a multiplexer (MUX) part 24 for selecting output signals of the P decoding part 20 and the N decoding part 22. The P decoding part 20 includes n P decoders for converting the n data Data simultaneously input from the latch portion 16 into the positive analog data AData using positive gamma voltages from the gamma voltage part 12. The N decoding part 22 includes n N decoders for converting the n data Data simultaneously input from the latch portion 16 into the negative analog data AData using negative gamma voltages from the gamma voltage part 12. The multiplexer part 24 includes n multiplexers for selectively outputting the positive analog data AData from the P decoder 20 or the negative analog data AData from the N decoder 22 in response to the polarity control signal POL from the signal generator 10.
The output buffer portion 26 includes n output buffers having voltage followers, etc. connected in series to the respective the data lines DL1 through DLn. The n output buffers make a signal buffering of the analog data AData from the DAC 18 and apply them to the data lines DL1 through DLn.
The related art LCD employs the DAC 18, which is supplied with the positive and negative gamma voltages from the gamma voltage part 12, to convert the digital data Data output from the timing controller 8 into the analog data Adata and apply them to the LCD panel 2. FIG. 5 is a waveform diagram illustrating an analog data supplied to the LCD panel 2 of FIG. 1. As shown in FIG. 5, the LCD panel 2 displays a desired picture by the analog data AData between a black and a white supplied to the liquid crystal cell 7 during one frame period (i.e., 16.7 ms).
The related art LCD requires 256 positive gamma voltages V0 through V255 having different voltage levels as well as 256 negative gamma voltages, and supplies them to the DAC 18 of the data driver 4 to display 8-bit data Data on the LCD panel 2 during one frame period (i.e., 16.7 ms) using a frame frequency Vsync of 60 Hz. Thus, the gamma voltage part 12 of each of the data driving ICs occupies a large area because the length of the internal R-String becomes very long by generating 256 positive gamma voltages V0 through V255 having different voltage levels and 256 negative gamma voltages. As a result, the related art LCD has a problem in that an area for arranging the data driver 4 having the data driving ICs is enlarged due to a large size of the gamma voltage part 12 of each data driving IC.